The present invention relates to a semiconductor device and a manufacturing technique thereof, particularly to a technique effective when applied to a semiconductor device having a power MISFET (Metal Insulator Semiconductor Field Effect Transistor).
In a vertical MOS transistor with a trench structure, which has a p type conductivity well diffusion layer and an n type conductivity source diffusion layer stacked in the network form over the surface of an n type conductivity semiconductor substrate, and a gate buried in an insulating film of a trench between these diffusion layers, there is disclosed, for example, a technique of heightening the breakdown voltage of the vertical MOS transistor by disposing a deep p type diffusion layer at the lower center of the source diffusion layer to cover the trench with a depletion layer upon application of a voltage between the drain and source, and disposing a p type guard ring at the periphery of the chip to promote extension of the depletion layer in the vicinity of the chip surface (refer to Patent Document 1, for example).
Also disclosed is the structure of a trench gate type MOS transistor in Japanese Patent Application Laid-Open No. 2001-168329, 2002-353452, Hei 10(1998)-173175, Hei 8(1996)-204194, Hei 6(1994)-204483, Hei 10(1998)-56174 and 2002-231944 (refer to Patent Documents 2, 3, 4, 5, 6, 7 and 8).    Patent Document 1: Japanese Patent Application Laid-Open No. Hei 6(1994)-151867    Patent Document 2: Japanese Patent Application Laid-Open No. 2001-168329    Patent Document 3: Japanese Patent Application Laid-Open No. 2002-353452    Patent Document 4: Japanese Patent Application Laid-Open No. Hei 10(1998)-173175    Patent Document 5: Japanese Patent Application Laid-Open No. Hei 8(1996)-204194    Patent Document 6: Japanese Patent Application Laid-Open No. Hei 6(1994)-204483    Patent Document 7: Japanese Patent Application Laid-Open No. Hei 10(1998)-56174    Patent Document 8: Japanese Patent Application Laid-Open No. 2002-231944